1. Field of the Invention
The present invention relates to an address generator in the demodulator of an optical disk system and, more particularly, to an address generator of the memory necessary for detecting and correcting an error in the signal which is recovered from a recording medium and which is eight-to-fourteen modulation (EFM) demodulated, for converting an error corrected digital signal into an analog signal.
Korean Patent Application No. 93-6740 is incorporated herein by reference for all purposes.
2. Discussion of Related Art
As shown in FIG. 1, a demodulator for a conventional optical disk system or compact disc player (a CDP) includes a disk motor 12 for rotating a disk 10, a disk servo 14 for controlling the rotation speed of the disk motor 12, a microcomputer 16 for controlling the disk servo and the overall demodulator, a display 18 for displaying information of the microcomputer 16, a switch 20 for operating the microcomputer 16, an optical pick-up 22 for reading information recorded onto the disk 10, a demodulator 24 for EFM demodulating the output signal of the optical pick-up 22, thus restoring the demodulated signal into original data symbols and then supplying the restored signal to the disk servo 14 and the microcomputer 16, a RAM 30 for storing the output signal of the demodulator 24, an error correction coder (ECC) 28 for reading the EFM demodulated signal stored in the RAM 30, performing error detection and correction and again storing the corrected data in RAM 30, a digital-to-analog (D/A) convertor 34 for reading the EFM demodulated signal which is stored in RAM 30, whose error has been corrected, and then converting it into an analog signal, an address generator 32 for generating a recording address of the EFM demodulated signal, a reading address of the EFM demodulated signal for error detection and correction, a recording address for storing the result of the error correction, and a reading address for converting the error-corrected EFM demodulated signal into analog form, and a low-pass filter 36 for eliminating the noise of the output signal of the D/A convertor 34 and outputting the signal as two channels L and R.
FIG. 2 is a systematic diagram of the encoder implementing a circular interleave Reed-Solomon code (CIRC) method used in the modulator of a conventional CDP, wherein the modulated data consists of two sets of six samples each, e.g., L and R channels, making twelve samples of an audio signal expressed as sixteen bits forming a sampling unit. Each of the sixteen bits of data is divided into upper and lower eight bits. Each of these eight bits of data is treated as one symbol (or word), e.g., twelve samples form 24 symbols.
A cross-over time delay 40 delays the data of the even samplings from the leading symbol of the 24 symbols by two symbols, crosses the 24 symbols and arranges the data symbols so that it is separated by a predetermined interval. The thus-crossed 24 data symbols are supplied to a C2 encoder 42, which forms a first error correction code C2 from the 24 data symbols where C2 denotes a Reed-Solomon code whose redundancy is four (where n equals 28 and k equals 24, and the minimum distance is five). Here, the parity of code C2 is represented by Q. A first check symbol row, i.e., four symbols of Q parity, is located in the middle of the 24 data symbols.
An interleaver 44 differentially delays and interleaves 24 symbols with four data symbols of Q parity, each by a different amount, thus creating 28 symbols in total. The differential delay operation is performed starting from the second symbol, i.e., excludes the first symbol, which results in the sequential delay amounts of 1D, 2D, 3D . . . , and 27D. Here, the primary unit D corresponds to a predetermined delay amount of four symbols.
A C1 encoder 46 forms a second error correction code C1 from the 28 data symbols differentially delayed by interleaver 44. C1 denotes a Reed-Solomon code whose redundancy is four (where n equals 32 and k equals 28, and whose minimum distance is five). It will be noted that the parity of C1 is represented by P. A second check symbol row, i.e., four symbols of P parity, is arranged next to last symbol among the 28 symbols.
A scrambler 48 delays the odd numbered time data symbols among the 28 symbols and four data symbols of P parity by one symbol, and generates all 32 data symbols, to thereby complete an encoding operation.
FIG. 3 is a systematic diagram of the corresponding decoder for implementing the CIRC method used in ECC 28 (CIRC) shown in FIG. 1. With respect to the 32 data symbols encoded by the CIRC method encoder shown in FIG. 2, the data symbols are processed in the reverse of the encoding order and, at the same time, the error detected by P and Q parities is corrected to thereby restore the original data symbols.
Referring to FIG. 3, 32 data symbols expressed in terms of W, P and Q, i.e., data rows, are recovered from the optical disk and demodulated. Here, the 24 data symbols expressed in terms of W, i.e., data symbol rows, represents audio data, and the data expressed in terms of P and Q, i.e., the first and second check symbol rows, contain parity data for detecting and correcting errors. The 32 data symbols are supplied to a descrambler 50, which delays the even numbered time data symbols from the leading data by one symbol in order to undo the scrambling of the scrambled 32 data symbols.
Since the magnitude of the groove formed on an optical disk in a CDP can be expressed as eight bits or less, an 8-bit signal processing unit is used, with the eight bits being treated as one symbol. Thus, the errors due to the groove of the optical disk exist largely as one symbol units. However, if there is a fault between symbols, an error of two symbols may be generated. Therefore, in order to scatter the occurrence of such a successive error, a delay of one symbol unit is performed, which is called scramble processing. At the time of reproduction, in order to undo the scrambling, a descramble processing is performed. It should be noted that the logic states of the four data symbols of Q and P parities are inverted by eight inverters.
A C1 decoder 52 detects burst errors in the residual 28 data symbols by way of four data symbols of P parity among the 32 data symbols and corrects some of the random errors at the same time. The error correction generates four syndromes by a parity check matrix, i.e., a Reed-Solomon code, each having the ability to correct only one symbol. If two or more symbol errors are generated, the data block is determined as having an uncorrectable error and the 28 symbols are transmitted to the next stage without being corrected. Here, pointers or flags (of at least one bit) are assigned to every symbol of all the data rows so as to indicate the presence or absence of an error.
A deinterleaver 54 differentially delays 28 data symbols transmitted from the C1 decoder 52 and thereby reverses the interleaving operation discussed above. In other words, since the errors generated during the reproduction of an optical disk are mostly due to scratches, dust or dirt, once an error is generated, several adjacent symbols are damaged at the same time. If many symbols are damaged within the same data block, error detection or correction becomes impossible. Therefore, at the time of recording, the symbols within one data block are separated and recorded in different data blocks. Then, at the time of reproduction, the separated symbols are restored to their original data block position, which is called deinter-leaving.
A C2 decoder 56 generates four syndromes from the Reed-Solomon code and input 28 symbols of data by using four data symbols of Q parity among the 28 data symbols restored into the original data block position after the interleaving is undone. Here, the 28 symbols are all delayed by the same delay time of 27D. It should be noted that C2 decoder 56 corrects a maximum of four symbol errors.
An inverse cross-over time delay 58 crosses over 24 data symbols supplied from the C2 decoder 56 with one another in order to restore them to the original data block position and delays two-symbols of undelayed data symbols by a two-symbol period in order to restore the symbol adjacent data with respect to a time axis, which were previously separated by a two-symbol delay process at the time of encoding, to the original position. Such a delay serves to prevent the output of uncorrectable error data continuously at the time of reproduction.
FIG. 4 is a block diagram of a conventional address generator 32 shown in FIG. 1, wherein an EFM counter 60 counts the counter pulse of the EFM data output from the microcomputer 16 and thereby generates a symbol address of the EFM demodulated signal. An EFM ROM 63 is a memory, which is addressed by EFM counter 60, for pre-storing the symbol address of the EFM demodulated signal. An ECC counter 61 counts the counter pulses of the C1 and C2 data and the C1 and C2 flags output from ECC 28 (of FIG. 1), and thereby generates symbol addresses for each of the C1 and C2 data and flags, respectively. ECC ROM1 64, ECC ROM2 65, ECC ROM3 66 and ECC ROM4 67 are memories, which are addressed by the ECC counter 61, for pre-storing each symbol address or flag address for the C1 and C2 data and flags, respectively. A D/A converter (DAC) counter 62 counts the counter pulses of the data output from the microcomputer 16 and thereby generates the symbol address or flag address of the output data. DAC ROM 68, which is a memory addressed by the D/A converter counter 62, pre-stores the symbol address or flag address of the output data. A multiplexer 69 selectively outputs one from among the symbol addresses of EFM ROM 63, ECC ROM1 64, ECC ROM2 65, ECC ROM3 66, ECC ROM4 67 and DAC ROM 68 to an adder 71, which also receives a frame address of one frame unit from base counter 70. Adder 71 adds the symbol address or flag address output from the multiplexer 69 and the frame address output from the base counter 70 and then supplies the result as a final address. RAM 72 stores a signal according to the final address output from the adder 71.
However, since the aforementioned conventional address generator calculates the memory address of each data symbol by using a large amount of ROM memory, e.g., by the look-up table method, chip size is increased. Thus, the overall reliability of the chips is reduced and the signal processing speed is also lowered.